Analog Emulation

Simulation time is a major bottleneck in the chip design process.  For purely digital designs, FPGA emulation is often used to speed up simulations, but it is not straightforward to use such an approach for analog/mixed-signal (AMS) designs because analog blocks cannot be directly mapped to an FPGA’s programmable logic.  In light of that issue, we are developing strategies to model analog blocks within the context of FPGA emulation, along with an open-source framework that makes it easy to apply those strategies.  The framework consists of a Python-based synthesizable model generator, as well as CAD tool automation that provides a simulator-like interface to FPGA boards.  Preliminary results show that our framework can provide a speedup of over three orders of magnitude when applied to a full AMS chip design, as compared to behavioral RTL simulations, which are themselves orders of magnitude faster than SPICE simulation.