DaVE

DaVE is a family of tools that together form a "big Digital, little analog" Verification Environment.

As devices continue to scale, it becomes more common to design chips with more complex digital compensation for limited analog performance. To address this need, DaVE tools are specifically designed to help simulate circuits that contain significant digital logic interacting with small analog blocks. Because the small analog pieces prevent the use of fast fully-digital simulators, our goal is to replace analog blocks with digital models that behave exactly the same way. This modeling process is widely used, but our tools make the process easier in a variety of ways: some help with analysis of the analog block (mProbo), others make hand-writing the model faster (mLingua), while others automate the model-creation process to reduce human effort and human error (mGenero, fixture).

mLingua:

A Verilog library with useful components for building CPU-optimized models of analog blocks. mLingua blocks use dynamic timestepping to meet a specified error while creating few update events. Although dynamic timesteps are difficult to compute on an FPGA they optimize performance on a CPU, where events are processed one at a time. Additionally, basing the timesteps on a set error threshold allows the model writer to put the model accuracy exactly where they want it for the best performance/accuracy tradeoff, without requiring them to think about the underlying timestep model.

mProbo:

A tool for analyzing spice models. Given a spice circuit and some information about that circuit, mProbo will automatically generate and run a spice testbench to measure the circuit’s input-output relationship. The inputs and outputs are considered in the domain specified by the user (e.g. voltage, phase, frequency) and linear regression is done between the inputs and output values in those domains. This basic model can be extended by adding more inputs that tweak the values, allowing different modes of operation, and fitting higher-order terms.

mGenero:

A tool for creating parameterizable verilog models. One author can write a templatized Verilog model for a specific type of circuit. When a user has a specific instance of that type of circuit, mGenero takes the templatized model and parameters specific to the user’s instance and creates the appropriate Verilog model. Often the templatized model is written with the mLingua library, and the parameters specific to the user’s instance are extracted using mProbo.

fixture:

This tool, currently under development, is essentially a re-write of mProbo with two major differences: 1) it uses fault (https://github.com/leonardt/fault) to describe testbenches so the circuit analysis is portable across various simulators, and even portable across spice and Verilog models. 2) It is designed so that developers can create new templates without a deep understanding of all the tool’s internals, which makes it easier to develop a large template library.

More information about mLingua, mProbo, and mGenero, as well as the tools themselves, can be found at their Github page: https://github.com/StanfordVLSI/DaVE.

The most recent version of fixture can be found at https://github.com/standanley/fixture, and more information can be found by emailing the developer at dstanley@Stanford.edu .