Validation Tools

Design validation is one of most important parts of digital system design. As the system gets more complex and heterogeneous, more and more engineering efforts have been spent on debugging and validation. Although there is a growing interest to design hardware with high-level hardware generator frameworks, how to debug and verify the generated RTL code remains an open question, since traditional EDA tools are not designed for machine-generated code.

Our research focuses on improving validation productivity by providing automatic verification and debugging tools for hardware generator frameworks. Currently there are two major projects in this area: automatic FSM verification and source-level debugging.

Machine-generated RTL code does not always obey RTL coding styles that are required for hard-written RTL designs, making it difficult for existing validation tools to extract and verify FSM. Our research uses control-flow graph analysis on generated RTL and extracts control logic. This leads to automatic FSM coverage and verification on generated RTL and sometimes even improves synthesis quality.

While hardware generator frameworks improve front-end design productivity using high-level languages such as Scala and Python, they introduce a level of indirection as compilers need to translate high-level languages into RTL code. Since verification tools only consume RTL designs, debugging hardware generated from high-level languages can be difficult due to language semantic difference and compiler optimization. Our research offers a debugging infrastructure that allows hardware generator frameworks exchange debugging information with the simulator. As a result, users can debug the design in the original source code, even though the simulation is done at the RTL level. The debugging infrastructure is non-intrusive and supports all major commercial simulators. We are improving the infrastructure to support more hardware generator frameworks.